diff options
| author | Paul Berry <stereotype441@gmail.com> | 2013-03-08 12:03:10 -0800 |
|---|---|---|
| committer | Andreas Boll <andreas.boll.dev@gmail.com> | 2013-04-17 12:56:03 +0200 |
| commit | 31ebe4004cacb34c738bf6954f50fff6c637411b (patch) | |
| tree | 4dc3710e6ff35d06d7e42ac4ed214a6add9c6729 | |
| parent | 6b13fd4d3b73f539de91842cc13500af06db4249 (diff) | |
i965: Apply depthstencil alignment workaround when doing fast clears.
Fast depth clears have the same depth/stencil alignment requirements
as other drawing operations. Therefore, we need to call
brw_workaround_depthstencil_alignment() from both the clear and
drawing paths.
Without this fix, we get image corruption if the following conditions
hold: (a) the first ever drawing operation to a depth miplevel (or the
first drawing operation after having used the texture for sampling) is
a clear, (b) the depth miplevel has a size that is eligible for fast
depth clears, and (c) the depth miplevel has an offset within the
miptree that isn't 8x8 aligned.
Fixes piglit "depthstencil-render-miplevels" tests with size 273.
NOTE: This is a candidate for stable branches
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit c5d5827951fb321a58cc781b4e386551035ebf1a)
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clear.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index ce40e52d46..7a8d4027af 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -40,6 +40,8 @@ #include "intel_mipmap_tree.h" #include "intel_regions.h" +#include "brw_context.h" + #define FILE_DEBUG_FLAG DEBUG_BLIT static const char *buffer_names[] = { @@ -207,7 +209,8 @@ brw_fast_clear_depth(struct gl_context *ctx) static void brw_clear(struct gl_context *ctx, GLbitfield mask) { - struct intel_context *intel = intel_context(ctx); + struct brw_context *brw = brw_context(ctx); + struct intel_context *intel = &brw->intel; if (!_mesa_check_conditional_render(ctx)) return; @@ -217,6 +220,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) } intel_prepare_render(intel); + brw_workaround_depthstencil_alignment(brw); if (mask & BUFFER_BIT_DEPTH) { if (brw_fast_clear_depth(ctx)) { |