Add test for sideport memory on IGP.

When we have side port memory we must not map K8_FB_LOCATION.

4 files changed, 79 insertions, 23 deletions

diff --git a/src/rhd_driver.c b/src/rhd_driver.c
index 8cd0170..c34fcb9 100644
--- a/src/rhd_driver.c
+++ b/src/rhd_driver.c
@@ -1511,11 +1511,11 @@ rhdMapFB(RHDPtr rhdPtr)
     rhdPtr->FbBase = NULL;
 
 #ifdef XSERVER_LIBPCIACCESS
-	rhdPtr->FbPCIAddress = rhdPtr->PciInfo->regions[RHD_FB_BAR].base_addr;
-	rhdPtr->FbMapSize = rhdPtr->PciInfo->regions[RHD_FB_BAR].size;
+    rhdPtr->FbPCIAddress = rhdPtr->PciInfo->regions[RHD_FB_BAR].base_addr;
+    rhdPtr->FbMapSize = rhdPtr->PciInfo->regions[RHD_FB_BAR].size;
 #else
-	rhdPtr->FbPCIAddress = rhdPtr->PciInfo->memBase[RHD_FB_BAR];
-	rhdPtr->FbMapSize = 1 << rhdPtr->PciInfo->size[RHD_FB_BAR];
+    rhdPtr->FbPCIAddress = rhdPtr->PciInfo->memBase[RHD_FB_BAR];
+    rhdPtr->FbMapSize = 1 << rhdPtr->PciInfo->size[RHD_FB_BAR];
 #endif
 
     /* some IGPs are special cases */
@@ -1540,6 +1540,10 @@ rhdMapFB(RHDPtr rhdPtr)
 	    option = X_CONFIG;
 	    SetIGPMemory = rhdPtr->unverifiedFeatures.val.bool;
 	}
+	if (SetIGPMemory && RHD_MC_IGP_SideportMemoryPresent(rhdPtr)) {
+	    SetIGPMemory = FALSE;
+	    option = X_DEFAULT;
+	}
 	if (SetIGPMemory) {
 	    xf86DrvMsg(rhdPtr->scrnIndex, option, "Mapping IGP memory @ 0x%8.8x\n",rhdPtr->FbPhysAddress);
 	    rhdPtr->FbMapSize = pScrn->videoRam * 1024;
@@ -2238,7 +2242,7 @@ _RHDReadMC(int scrnIndex, CARD32 addr)
     RHDPtr rhdPtr = RHDPTR(xf86Screens[scrnIndex]);
     CARD32 ret;
 
-    if (rhdPtr->ChipSet < RHD_RS690 || rhdPtr->ChipSet == RHD_RS780) {
+    if (rhdPtr->ChipSet < RHD_RS690) {
 	_RHDRegWrite(scrnIndex, MC_IND_INDEX, addr);
 	ret = _RHDRegRead(scrnIndex, MC_IND_DATA);
     } else if (rhdPtr->ChipSet == RHD_RS600) {
@@ -2246,11 +2250,11 @@ _RHDReadMC(int scrnIndex, CARD32 addr)
 	ret = _RHDRegRead(scrnIndex, RS60_MC_NB_MC_DATA);
     } else if (rhdPtr->ChipSet == RHD_RS690 || rhdPtr->ChipSet == RHD_RS740) {
 #ifdef XSERVER_LIBPCIACCESS
-	CARD32 data = addr & ~RS69_C_IND_WR_EN;
+	CARD32 data = addr & ~RS69_MC_IND_WR_EN;
 	pci_device_cfg_write(rhdPtr->NBPciInfo, &(data), RS69_MC_INDEX, 4, NULL);
 	pci_device_cfg_read(rhdPtr->NBPciInfo, &ret, RS69_MC_DATA, 4, NULL);
 #else
-	pciWriteLong(rhdPtr->NBPciTag, RS69_MC_INDEX, addr & ~RS69_C_IND_WR_EN);
+	pciWriteLong(rhdPtr->NBPciTag, RS69_MC_INDEX, addr & ~RS69_MC_IND_WR_EN);
 	ret = pciReadLong(rhdPtr->NBPciTag, RS69_MC_DATA);
 #endif
     } else {
@@ -2259,7 +2263,7 @@ _RHDReadMC(int scrnIndex, CARD32 addr)
 	pci_device_cfg_write(rhdPtr->NBPciInfo, &(data), RS78_NB_MC_IND_INDEX, 4, NULL);
 	pci_device_cfg_read(rhdPtr->NBPciInfo, &ret, RS78_NB_MC_IND_DATA, 4, NULL);
 #else
-	pciWriteLong(rhdPtr->NBPciTag, RS78_NB_MC_IND_INDEX, addr & ~RS78_MC_IND_WR_EN);
+	pciWriteLong(rhdPtr->NBPciTag, RS78_NB_MC_IND_INDEX, (addr & ~RS78_MC_IND_WR_EN));
 	ret = pciReadLong(rhdPtr->NBPciTag, RS78_NB_MC_IND_DATA);
 #endif
     }
@@ -2285,10 +2289,10 @@ _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data)
 	_RHDRegWrite(scrnIndex, RS60_MC_NB_MC_DATA, data);
     } else if (rhdPtr->ChipSet == RHD_RS690 || rhdPtr->ChipSet == RHD_RS740) {
 #ifdef XSERVER_LIBPCIACCESS
-	pci_device_cfg_write(rhdPtr->NBPciInfo, &addr | RS69_C_IND_WR_EN, RS69_MC_INDEX, 4, NULL);
+	pci_device_cfg_write(rhdPtr->NBPciInfo, &addr | RS69_MC_IND_WR_EN, RS69_MC_INDEX, 4, NULL);
 	pci_device_cfg_write(rhdPtr->NBPciInfo, &data, RS69_MC_DATA, 4, NULL);
 #else
-	pciWriteLong(rhdPtr->NBPciTag, RS69_MC_INDEX, addr | RS69_C_IND_WR_EN);
+	pciWriteLong(rhdPtr->NBPciTag, RS69_MC_INDEX, addr | RS69_MC_IND_WR_EN);
 	pciWriteLong(rhdPtr->NBPciTag, RS69_MC_DATA, data);
 #endif
 
@@ -2433,6 +2437,8 @@ rhdProcessOptions(ScrnInfoPtr pScrn)
 			&rhdPtr->tvModeName, NULL);
     RhdGetOptValString (rhdPtr->Options, OPTION_SCALE_TYPE,
 		       &rhdPtr->scaleTypeOpt, "default");
+    RhdGetOptValBool   (rhdPtr->Options, OPTION_UNVERIFIED_FEAT,
+			&rhdPtr->unverifiedFeatures, FALSE);
 
     rhdAccelOptionsHandle(pScrn);
 
diff --git a/src/rhd_mc.c b/src/rhd_mc.c
index fa5b6ac..b49f16b 100644
--- a/src/rhd_mc.c
+++ b/src/rhd_mc.c
@@ -595,3 +595,25 @@ RHDMCDestroy(RHDPtr rhdPtr)
     rhdPtr->MC = NULL;
 }
 
+Bool
+RHD_MC_IGP_SideportMemoryPresent(RHDPtr rhdPtr)
+{
+    Bool Present = FALSE;
+
+    RHDFUNC(rhdPtr);
+
+    switch (rhdPtr->ChipSet) {
+	case RHD_RS690:
+	case RHD_RS740:
+	    Present = (RHDReadMC(rhdPtr, RS69_MC_MISC_UMA_CNTL) & RS69_SIDE_PORT_PRESENT_R) != 0;
+	    break;
+	case RHD_RS780:
+	    Present = (RHDReadMC(rhdPtr, RS78_MC_MISC_UMA_CNTL) & RS78_SIDE_PORT_PRESENT_R) != 0;
+	    break;
+	default:
+	    break;
+    }
+    xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "IPG sideport memory %s present.\n", Present ? "" : "not");
+
+    return Present;
+}
diff --git a/src/rhd_mc.h b/src/rhd_mc.h
index aaa1c84..d918411 100644
--- a/src/rhd_mc.h
+++ b/src/rhd_mc.h
@@ -1,8 +1,8 @@
 /*
- * Copyright 2007  Luc Verhaegen <lverhaegen@novell.com>
- * Copyright 2007  Matthias Hopf <mhopf@novell.com>
- * Copyright 2007  Egbert Eich   <eich@novell.com>
- * Copyright 2007  Advanced Micro Devices, Inc.
+ * Copyright 2007, 2008  Luc Verhaegen <lverhaegen@novell.com>
+ * Copyright 2007, 2008  Matthias Hopf <mhopf@novell.com>
+ * Copyright 2007, 2008  Egbert Eich   <eich@novell.com>
+ * Copyright 2007, 2008  Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,11 +25,13 @@
 #ifndef RHD_MC_H
 # define RHD_MC_H
 
-void RHDMCInit(RHDPtr rhdPtr);
-void RHDMCDestroy(RHDPtr rhdPtr);
-void RHDSaveMC(RHDPtr rhdPtr);
-void RHDRestoreMC(RHDPtr rhdPtr);
-void RHDMCSetup(RHDPtr rhdPtr);
-Bool RHDMCIdle(RHDPtr rhdPtr, CARD32 count);
+extern void RHDMCInit(RHDPtr rhdPtr);
+extern void RHDMCDestroy(RHDPtr rhdPtr);
+extern void RHDSaveMC(RHDPtr rhdPtr);
+extern void RHDRestoreMC(RHDPtr rhdPtr);
+extern void RHDMCSetup(RHDPtr rhdPtr);
+extern Bool RHDMCIdle(RHDPtr rhdPtr, CARD32 count);
+
+extern Bool RHD_MC_IGP_SideportMemoryPresent(RHDPtr rhdPtr);
 
 #endif /* RHD_MC_H */
diff --git a/src/rhd_regs.h b/src/rhd_regs.h
index 9fca4bb..740cdc7 100644
--- a/src/rhd_regs.h
+++ b/src/rhd_regs.h
@@ -767,7 +767,7 @@ enum RS69_DDIA_PCIE_LINK_CONTROL3_BITS {
 
 enum RS69_MC_INDEX_BITS {
     RS69_MC_IND_ADDR = (0x1 << 0),
-    RS69_C_IND_WR_EN = (0x1 << 9)
+    RS69_MC_IND_WR_EN = (0x1 << 9)
 };
 
 enum RS60_MC_NB_MC_INDEX_BITS {
@@ -777,11 +777,29 @@ enum RS60_MC_NB_MC_INDEX_BITS {
 
 enum _rs690MCRegs {
     RS69_K8_FB_LOCATION		=	0x1E,
+    RS69_MC_MISC_UMA_CNTL	=	0x5f,
     RS69_MC_SYSTEM_STATUS 	=	0x90,  /* (RW) */
     RS69_MCCFG_FB_LOCATION		=	0x100,
     RS69MCCFG_AGP_LOCATION		=	0x101
 };
 
+enum RS69_MC_MISC_UMA_CNTL_BITS {
+    RS69_K8_40BIT_ADDR_EXTENSION = (0x1 << 0),
+    RS69_GART_BYPASS             = (0x1 << 8),
+    RS69_GFX_64BYTE_MODE         = (0x1 << 9),
+    RS69_GFX_64BYTE_LAT          = (0x1 << 10),
+    RS69_GTW_COHERENCY           = (0x1 << 15),
+    RS69_READ_BUFFER_SIZE        = (0x1 << 16),
+    RS69_HDR_ROUTE_TO_DSP        = (0x1 << 24),
+    RS69_GTW_ROUTE_TO_DSP        = (0x1 << 25),
+    RS69_DSP_ROUTE_TO_GFX        = (0x1 << 26),
+    RS69_USE_HDPW_LAT_INIT       = (0x1 << 27),
+    RS69_USE_GFXW_LAT_INIT       = (0x1 << 28),
+    RS69_MCIFR_COHERENT          = (0x1 << 29),
+    RS69_NON_SNOOP_AZR_AIC_BP    = (0x1 << 30),
+    RS69_SIDE_PORT_PRESENT_R     = (0x1 << 31)
+};
+
 enum _rs600MCRegs {
     RS60_MC_SYSTEM_STATUS	=       0x0,
     RS60_NB_FB_LOCATION		=	0xa
@@ -793,7 +811,7 @@ enum _rs780NBRegs {
 };
 
 enum RS78_NB_IND_INDEX_BITS {
-    RS78_RS78_NB_MC_IND_INDEX = (0xffff << 0),
+    RS78_NB_MC_IND_INDEX_MASK = (0xffff << 0),
     RS78_MC_IND_SEQ_RBS_0     = (0x1 << 16),
     RS78_MC_IND_SEQ_RBS_1     = (0x1 << 17),
     RS78_MC_IND_SEQ_RBS_2     = (0x1 << 18),
@@ -808,7 +826,8 @@ enum RS78_NB_IND_INDEX_BITS {
 enum _rs780MCRegs {
     RS78_MC_SYSTEM_STATUS	=	0x0,
     RS78_MC_FB_LOCATION		=	0x10,
-    RS78_K8_FB_LOCATION		=	0x11
+    RS78_K8_FB_LOCATION		=	0x11,
+    RS78_MC_MISC_UMA_CNTL       =       0x12
 };
 
 enum RS6X_MC_SYSTEM_STATUS_BITS {
@@ -826,6 +845,13 @@ enum RS6X_MC_SYSTEM_STATUS_BITS {
 	RS6X_RESERVED20_SYSTEM_STATUS	 = (0xfff << 20)
 };
 
+enum RS78_MC_MISC_UMA_CNTL_BITS {
+    RS78_K8_40BIT_ADDR_EXTENSION = ( 0x1 << 0),
+    RS78_BANKGROUP_SEL           = ( 0x1 << 8),
+    RS78_CNTL_SPARE              = ( 0x1 << 15),
+    RS78_SIDE_PORT_PRESENT_R     = ( 0x1 << 31)
+};
+
 enum R5XX_MC_STATUS_BITS {
     R5XX_MEM_PWRUP_COMPL = (0x1 << 0),
     R5XX_MC_IDLE	    = (0x1 << 1)