diff options
| author | Yannick Fertre <yannick.fertre@st.com> | 2017-03-28 11:44:49 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-04-06 23:24:06 +0200 |
| commit | 966fea78adf23339fa73d6cdbcd9cd96a57c92b7 (patch) | |
| tree | 369ba6d8b09c3f68a5dd3eb6631a9e4a5b9b3484 | |
| parent | 2db496753e3a7da6117266d61782456511896c66 (diff) | |
drm/panel: simple: Add support for Ampire AM-480272H3TMQW-T01H
Add simple-panel support for the Ampire AM-480272H3TMQW-T01H, which is a
4.3" WQVGA panel.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/gpu/drm/panel/panel-simple.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 89eb0422821c..2a5536685fe8 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -386,6 +386,31 @@ static void panel_simple_shutdown(struct device *dev) panel_simple_disable(&panel->base); } +static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { + .clock = 9000, + .hdisplay = 480, + .hsync_start = 480 + 2, + .hsync_end = 480 + 2 + 41, + .htotal = 480 + 2 + 41 + 2, + .vdisplay = 272, + .vsync_start = 272 + 2, + .vsync_end = 272 + 2 + 10, + .vtotal = 272 + 2 + 10 + 2, + .vrefresh = 60, + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, +}; + +static const struct panel_desc ampire_am_480272h3tmqw_t01h = { + .modes = &ire_am_480272h3tmqw_t01h_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 105, + .height = 67, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, +}; + static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { .clock = 33333, .hdisplay = 800, @@ -1808,6 +1833,9 @@ static const struct panel_desc urt_umsh_8596md_parallel = { static const struct of_device_id platform_of_match[] = { { + .compatible = "ampire,am-480272h3tmqw-t01h", + .data = &ire_am_480272h3tmqw_t01h, + }, { .compatible = "ampire,am800480r3tmqwa1h", .data = &ire_am800480r3tmqwa1h, }, { |