Convert CIO, DIO and VIO use to use defines from nvreg for index and data reg offsets

5 files changed, 129 insertions, 124 deletions

diff --git a/src/nv_bios.c b/src/nv_bios.c
index d8ea70f..acac708 100644
--- a/src/nv_bios.c
+++ b/src/nv_bios.c
@@ -34,7 +34,6 @@
 
 
 /* FIXME: put these somewhere */
-#define SEQ_INDEX VGA_SEQ_INDEX
 #define NV_CIO_CRE_44_HEADA 0x0
 #define NV_CIO_CRE_44_HEADB 0x3
 #define FEATURE_MOBILE 0x10
@@ -284,9 +283,9 @@ static bool nv_valid_idx_port(ScrnInfoPtr pScrn, uint16_t port)
 	 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
 	 * used for the port in question
 	 */
-	if (port == CRTC_INDEX_COLOR)
+	if (port == NV_CIO_CRX__COLOR)
 		return true;
-	if (port == SEQ_INDEX)
+	if (port == NV_VIO_SRX)
 		return true;
 
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -301,7 +300,7 @@ static bool nv_valid_port(ScrnInfoPtr pScrn, uint16_t port)
 	 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
 	 * used for the port in question
 	 */
-	if (port == VGA_ENABLE)
+	if (port == NV_VIO_VSE2)
 		return true;
 
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -366,9 +365,9 @@ static uint8_t nv_idx_port_rd(ScrnInfoPtr pScrn, uint16_t port, uint8_t index)
 	if (!nv_valid_idx_port(pScrn, port))
 		return 0;
 
-	if (port == SEQ_INDEX)
+	if (port == NV_VIO_SRX)
 		data = NVReadVgaSeq(pNv, crtchead, index);
-	else	/* assume CRTC_INDEX_COLOR */
+	else	/* assume NV_CIO_CRX__COLOR */
 		data = NVReadVgaCrtc(pNv, crtchead, index);
 
 	BIOSLOG(pScrn, "	Indexed IO read:  Port: 0x%04X, Index: 0x%02X, Head: 0x%02X, Data: 0x%02X\n",
@@ -390,7 +389,7 @@ static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint
 	 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
 	 * of the write, and to head1 after the write
 	 */
-	if (port == CRTC_INDEX_COLOR && index == NV_CIO_CRE_44 && data != NV_CIO_CRE_44_HEADB)
+	if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && data != NV_CIO_CRE_44_HEADB)
 		crtchead = 0;
 
 	LOG_OLD_VALUE(nv_idx_port_rd(pScrn, port, index));
@@ -399,13 +398,13 @@ static void nv_idx_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t index, uint
 
 	if (pNv->VBIOS.execute) {
 		still_alive();
-		if (port == SEQ_INDEX)
+		if (port == NV_VIO_SRX)
 			NVWriteVgaSeq(pNv, crtchead, index, data);
-		else	/* assume CRTC_INDEX_COLOR */
+		else	/* assume NV_CIO_CRX__COLOR */
 			NVWriteVgaCrtc(pNv, crtchead, index, data);
 	}
 
-	if (port == CRTC_INDEX_COLOR && index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
+	if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
 		crtchead = 1;
 }
 
@@ -417,7 +416,7 @@ static uint8_t nv_port_rd(ScrnInfoPtr pScrn, uint16_t port)
 	if (!nv_valid_port(pScrn, port))
 		return 0;
 
-	data = NVReadPRMVIO(pNv, crtchead, port);
+	data = NVReadPRMVIO(pNv, crtchead, NV_PRMVIO0_OFFSET + port);
 
 	BIOSLOG(pScrn, "	IO read:  Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
 		port, crtchead, data);
@@ -438,7 +437,7 @@ static void nv_port_wr(ScrnInfoPtr pScrn, uint16_t port, uint8_t data)
 
 	if (pNv->VBIOS.execute) {
 		still_alive();
-		NVWritePRMVIO(pNv, crtchead, port, data);
+		NVWritePRMVIO(pNv, crtchead, NV_PRMVIO0_OFFSET + port, data);
 	}
 }
 
@@ -1481,16 +1480,16 @@ static bool init_cr_idx_adr_latch(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offs
 	BIOSLOG(pScrn, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, BaseAddr: 0x%02X, Count: 0x%02X\n",
 		offset, crtcindex1, crtcindex2, baseaddr, count);
 
-	oldaddr = nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex1);
+	oldaddr = nv_idx_port_rd(pScrn, NV_CIO_CRX__COLOR, crtcindex1);
 
 	for (i = 0; i < count; i++) {
-		nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, baseaddr + i);
+		nv_idx_port_wr(pScrn, NV_CIO_CRX__COLOR, crtcindex1, baseaddr + i);
 
 		data = bios->data[offset + 5 + i];
-		nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex2, data);
+		nv_idx_port_wr(pScrn, NV_CIO_CRX__COLOR, crtcindex2, data);
 	}
 
-	nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex1, oldaddr);
+	nv_idx_port_wr(pScrn, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
 
 	return true;
 }
@@ -1519,8 +1518,8 @@ static bool init_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exec_
 	BIOSLOG(pScrn, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
 		offset, crtcindex, mask, data);
 
-	value = (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, crtcindex) & mask) | data;
-	nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, value);
+	value = (nv_idx_port_rd(pScrn, NV_CIO_CRX__COLOR, crtcindex) & mask) | data;
+	nv_idx_port_wr(pScrn, NV_CIO_CRX__COLOR, crtcindex, value);
 
 	return true;
 }
@@ -1542,7 +1541,7 @@ static bool init_zm_cr(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_ex
 	if (!iexec->execute)
 		return true;
 
-	nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, crtcindex, data);
+	nv_idx_port_wr(pScrn, NV_CIO_CRX__COLOR, crtcindex, data);
 
 	return true;
 }
@@ -1824,12 +1823,12 @@ static bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, i
 	/* no iexec->execute check by design */
 
 	/* on every card I've seen, this step gets done for us earlier in the init scripts
-	uint8_t crdata = nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01);
-	nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, crdata | 0x20);
+	uint8_t crdata = nv_idx_port_rd(pScrn, NV_VIO_SRX, 0x01);
+	nv_idx_port_wr(pScrn, NV_VIO_SRX, 0x01, crdata | 0x20);
 	*/
 
 	/* this also has probably been done in the scripts, but an mmio trace of
-	 * s3 resume shows nvidia doing it anyway (unlike the SEQ_INDEX write)
+	 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
 	 */
 	nv32_wr(pScrn, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
 
@@ -1887,14 +1886,14 @@ static bool init_configure_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset,
 
 	/* no iexec->execute check by design */
 
-	uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
+	uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
 	uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
 	uint32_t reg, data;
 
 	if (bios->major_version > 2)
 		return false;
 
-	nv_idx_port_wr(pScrn, SEQ_INDEX, 0x01, nv_idx_port_rd(pScrn, SEQ_INDEX, 0x01) | 0x20);
+	nv_idx_port_wr(pScrn, NV_VIO_SRX, 0x01, nv_idx_port_rd(pScrn, NV_VIO_SRX, 0x01) | 0x20);
 
 	if (bios->data[meminitoffs] & 1)
 		seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
@@ -1939,7 +1938,7 @@ static bool init_configure_clk(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset,
 
 	/* no iexec->execute check by design */
 
-	uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
+	uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (nv_idx_port_rd(pScrn, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
 	int clock;
 
 	if (bios->major_version > 2)
@@ -1975,7 +1974,7 @@ static bool init_configure_preinit(ScrnInfoPtr pScrn, bios_t *bios, uint16_t off
 	if (bios->major_version > 2)
 		return false;
 
-	nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
+	nv_idx_port_wr(pScrn, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
 
 	return true;
 }
@@ -2732,7 +2731,7 @@ static void rundigitaloutscript(ScrnInfoPtr pScrn, uint16_t scriptptr, struct dc
 	init_exec_t iexec = {true, false};
 
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "0x%04X: Parsing digital output script table\n", scriptptr);
-	nv_idx_port_wr(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_44,
+	nv_idx_port_wr(pScrn, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
 		       head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
 	NVWriteVgaCrtc5758(NVPTR(pScrn), head, 0, dcbent->index);
 	parse_init_table(pScrn, bios, scriptptr, &iexec);
@@ -3465,7 +3464,7 @@ bool get_pll_limits(ScrnInfoPtr pScrn, uint32_t limit_match, struct pll_lims *pl
 
 			if (((limit_match == NV_RAMDAC_VPLL || limit_match == VPLL1) && sel_clk & 0x20) ||
 			    ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
-				if (nv_idx_port_rd(pScrn, CRTC_INDEX_COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
+				if (nv_idx_port_rd(pScrn, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
 					pll_lim->refclk = 200000;
 				else
 					pll_lim->refclk = 25000;
diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index 831b54f..1a17985 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -1340,7 +1340,7 @@ static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 	int i;
 	NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 
-	NVWritePRMVIO(pNv, nv_crtc->head, VGA_MISC_OUT_W, regp->MiscOutReg);
+	NVWritePRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
 
 	for (i = 0; i < 5; i++)
 		NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
@@ -1464,7 +1464,7 @@ static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 	int i;
 	NVCrtcRegPtr regp = &state->crtc_reg[nv_crtc->head];
 
-	regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head, VGA_MISC_OUT_R);
+	regp->MiscOutReg = NVReadPRMVIO(pNv, nv_crtc->head, NV_PRMVIO_MISC__READ);
 
 	for (i = 0; i < 25; i++)
 		regp->CRTC[i] = NVReadVgaCrtc(pNv, nv_crtc->head, i);
@@ -1684,15 +1684,14 @@ static void nv_crtc_save_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 {
 	struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 	NVPtr pNv = NVPTR(crtc->scrn);
-	uint32_t mmiobase = nv_crtc->head ? NV_PRMDIO1_OFFSET : NV_PRMDIO0_OFFSET;
-	int i;
+	int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
 
-	VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
-	VGA_WR08(pNv->REGS, VGA_DAC_READ_ADDR + mmiobase, 0x0);
+	VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
+	VGA_WR08(pNv->REGS, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
 
 	for (i = 0; i < 768; i++) {
-		state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, VGA_DAC_DATA + mmiobase);
-		DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
+		state->crtc_reg[nv_crtc->head].DAC[i] = NV_RD08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset);
+		DDXMMIOH("nv_crtc_save_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
 	}
 
 	NVSetEnablePalette(pNv, nv_crtc->head, false);
@@ -1701,15 +1700,14 @@ static void nv_crtc_load_state_palette(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 {
 	struct nouveau_crtc *nv_crtc = to_nouveau_crtc(crtc);
 	NVPtr pNv = NVPTR(crtc->scrn);
-	uint32_t mmiobase = nv_crtc->head ? NV_PRMDIO1_OFFSET : NV_PRMDIO0_OFFSET;
-	int i;
+	int head_offset = nv_crtc->head * NV_PRMDIO_SIZE, i;
 
-	VGA_WR08(pNv->REGS, VGA_DAC_MASK + mmiobase, 0xff);
-	VGA_WR08(pNv->REGS, VGA_DAC_WRITE_ADDR + mmiobase, 0x0);
+	VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
+	VGA_WR08(pNv->REGS, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
 
 	for (i = 0; i < 768; i++) {
-		DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
-		NV_WR08(pNv->REGS, VGA_DAC_DATA + mmiobase, state->crtc_reg[nv_crtc->head].DAC[i]);
+		DDXMMIOH("nv_crtc_load_state_palette: head %d reg 0x%04x data 0x%02x\n", nv_crtc->head, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
+		NV_WR08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset, state->crtc_reg[nv_crtc->head].DAC[i]);
 	}
 
 	NVSetEnablePalette(pNv, nv_crtc->head, false);
diff --git a/src/nv_hw.c b/src/nv_hw.c
index 3f0f8a4..4681f93 100644
--- a/src/nv_hw.c
+++ b/src/nv_hw.c
@@ -98,20 +98,16 @@ void nv_write_tmds(NVPtr pNv, int or, int dl, uint8_t address, uint8_t data)
 
 void NVWriteVgaCrtc(NVPtr pNv, int head, uint8_t index, uint8_t value)
 {
-	uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET;
-
 	DDXMMIOH("NVWriteVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, value);
-	NV_WR08(pNv->REGS, CRTC_INDEX_COLOR + mmiobase, index);
-	NV_WR08(pNv->REGS, CRTC_DATA_COLOR + mmiobase, value);
+	NV_WR08(pNv->REGS, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
+	NV_WR08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
 }
 
 uint8_t NVReadVgaCrtc(NVPtr pNv, int head, uint8_t index)
 {
-	uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET;
-
-	NV_WR08(pNv->REGS, CRTC_INDEX_COLOR + mmiobase, index);
-	DDXMMIOH("NVReadVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, CRTC_DATA_COLOR + mmiobase));
-	return NV_RD08(pNv->REGS, CRTC_DATA_COLOR + mmiobase);
+	NV_WR08(pNv->REGS, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
+	DDXMMIOH("NVReadVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE));
+	return NV_RD08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
 }
 
 /* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
@@ -140,94 +136,86 @@ uint8_t NVReadVgaCrtc5758(NVPtr pNv, int head, uint8_t index)
 	return NVReadVgaCrtc(pNv, head, NV_CIO_CRE_58);
 }
 
-uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint16_t port)
+uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint32_t reg)
 {
 	/* Only NV4x have two pvio ranges */
-	uint32_t mmiobase = (head && pNv->Architecture == NV_ARCH_40) ? NV_PRMVIO1_OFFSET : NV_PRMVIO0_OFFSET;
+	if (head && pNv->Architecture == NV_ARCH_40)
+		reg += NV_PRMVIO_SIZE;
 
-	DDXMMIOH("NVReadPRMVIO: head %d reg %08x val %02x\n", head, port + mmiobase, NV_RD08(pNv->REGS, port + mmiobase));
-	return NV_RD08(pNv->REGS, port + mmiobase);
+	DDXMMIOH("NVReadPRMVIO: head %d reg %08x val %02x\n", head, reg, NV_RD08(pNv->REGS, reg));
+	return NV_RD08(pNv->REGS, reg);
 }
 
-void NVWritePRMVIO(NVPtr pNv, int head, uint16_t port, uint8_t value)
+void NVWritePRMVIO(NVPtr pNv, int head, uint32_t reg, uint8_t value)
 {
 	/* Only NV4x have two pvio ranges */
-	uint32_t mmiobase = (head && pNv->Architecture == NV_ARCH_40) ? NV_PRMVIO1_OFFSET : NV_PRMVIO0_OFFSET;
+	if (head && pNv->Architecture == NV_ARCH_40)
+		reg += NV_PRMVIO_SIZE;
 
-	DDXMMIOH("NVWritePRMVIO: head %d reg %08x val %02x\n", head, port + mmiobase, value);
-	NV_WR08(pNv->REGS, port + mmiobase, value);
+	DDXMMIOH("NVWritePRMVIO: head %d reg %08x val %02x\n", head, reg, value);
+	NV_WR08(pNv->REGS, reg, value);
 }
 
 void NVWriteVgaSeq(NVPtr pNv, int head, uint8_t index, uint8_t value)
 {
-	NVWritePRMVIO(pNv, head, VGA_SEQ_INDEX, index);
-	NVWritePRMVIO(pNv, head, VGA_SEQ_DATA, value);
+	NVWritePRMVIO(pNv, head, NV_PRMVIO_SRX, index);
+	NVWritePRMVIO(pNv, head, NV_PRMVIO_SR, value);
 }
 
 uint8_t NVReadVgaSeq(NVPtr pNv, int head, uint8_t index)
 {
-	NVWritePRMVIO(pNv, head, VGA_SEQ_INDEX, index);
-	return NVReadPRMVIO(pNv, head, VGA_SEQ_DATA);
+	NVWritePRMVIO(pNv, head, NV_PRMVIO_SRX, index);
+	return NVReadPRMVIO(pNv, head, NV_PRMVIO_SR);
 }
 
 void NVWriteVgaGr(NVPtr pNv, int head, uint8_t index, uint8_t value)
 {
-	NVWritePRMVIO(pNv, head, VGA_GRAPH_INDEX, index);
-	NVWritePRMVIO(pNv, head, VGA_GRAPH_DATA, value);
+	NVWritePRMVIO(pNv, head, NV_PRMVIO_GRX, index);
+	NVWritePRMVIO(pNv, head, NV_PRMVIO_GX, value);
 }
 
 uint8_t NVReadVgaGr(NVPtr pNv, int head, uint8_t index)
 {
-	NVWritePRMVIO(pNv, head, VGA_GRAPH_INDEX, index);
-	return NVReadPRMVIO(pNv, head, VGA_GRAPH_DATA);
+	NVWritePRMVIO(pNv, head, NV_PRMVIO_GRX, index);
+	return NVReadPRMVIO(pNv, head, NV_PRMVIO_GX);
 }
 
-#define CRTC_IN_STAT_1 0x3da
-
 void NVSetEnablePalette(NVPtr pNv, int head, bool enable)
 {
-	uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET;
-
-	VGA_RD08(pNv->REGS, CRTC_IN_STAT_1 + mmiobase);
-	VGA_WR08(pNv->REGS, VGA_ATTR_INDEX + mmiobase, enable ? 0 : 0x20);
+	VGA_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
+	VGA_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
 }
 
 static bool NVGetEnablePalette(NVPtr pNv, int head)
 {
-	uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET;
-
-	VGA_RD08(pNv->REGS, CRTC_IN_STAT_1 + mmiobase);
-	return !(VGA_RD08(pNv->REGS, VGA_ATTR_INDEX + mmiobase) & 0x20);
+	VGA_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
+	return !(VGA_RD08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
 }
 
 void NVWriteVgaAttr(NVPtr pNv, int head, uint8_t index, uint8_t value)
 {
-	uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET;
-
 	if (NVGetEnablePalette(pNv, head))
 		index &= ~0x20;
 	else
 		index |= 0x20;
 
-	NV_RD08(pNv->REGS, CRTC_IN_STAT_1 + mmiobase);
+	NV_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
 	DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", head, index, value);
-	NV_WR08(pNv->REGS, VGA_ATTR_INDEX + mmiobase, index);
-	NV_WR08(pNv->REGS, VGA_ATTR_DATA_W + mmiobase, value);
+	NV_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
+	NV_WR08(pNv->REGS, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
 }
 
 uint8_t NVReadVgaAttr(NVPtr pNv, int head, uint8_t index)
 {
-	uint32_t mmiobase = head ? NV_PRMCIO1_OFFSET : NV_PRMCIO0_OFFSET;
-
 	if (NVGetEnablePalette(pNv, head))
 		index &= ~0x20;
 	else
 		index |= 0x20;
 
-	NV_RD08(pNv->REGS, CRTC_IN_STAT_1 + mmiobase);
-	NV_WR08(pNv->REGS, VGA_ATTR_INDEX + mmiobase, index);
-	DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, VGA_ATTR_DATA_R + mmiobase));
-	return NV_RD08(pNv->REGS, VGA_ATTR_DATA_R + mmiobase);
+	NV_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
+	NV_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
+	DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE));
+	return NV_RD08(pNv->REGS, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
 }
 
 void NVVgaSeqReset(NVPtr pNv, int head, bool start)
@@ -1131,12 +1119,6 @@ uint32_t nv_pitch_align(NVPtr pNv, uint32_t width, int bpp)
 	return (width + mask) & ~mask;
 }
 
-#define VGA_SEQ_PLANE_WRITE     0x02
-#define VGA_SEQ_MEMORY_MODE     0x04
-#define VGA_GFX_PLANE_READ      0x04
-#define VGA_GFX_MODE            0x05
-#define VGA_GFX_MISC            0x06
-
 void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
 {
 	NVPtr pNv = NVPTR(pScrn);
@@ -1157,21 +1139,21 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
 	NVBlankScreen(pNv, 0, true);
 
 	/* save control regs */
-	misc = NVReadPRMVIO(pNv, 0, VGA_MISC_OUT_R);
-	seq2 = NVReadVgaSeq(pNv, 0, VGA_SEQ_PLANE_WRITE);
-	seq4 = NVReadVgaSeq(pNv, 0, VGA_SEQ_MEMORY_MODE);
-	gr4 = NVReadVgaGr(pNv, 0, VGA_GFX_PLANE_READ);
-	gr5 = NVReadVgaGr(pNv, 0, VGA_GFX_MODE);
-	gr6 = NVReadVgaGr(pNv, 0, VGA_GFX_MISC);
-
-	NVWritePRMVIO(pNv, 0, VGA_MISC_OUT_W, 0x67);
-	NVWriteVgaSeq(pNv, 0, VGA_SEQ_MEMORY_MODE, 0x6);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_MODE, 0x0);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_MISC, 0x5);
+	misc = NVReadPRMVIO(pNv, 0, NV_PRMVIO_MISC__READ);
+	seq2 = NVReadVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX);
+	seq4 = NVReadVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX);
+	gr4 = NVReadVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX);
+	gr5 = NVReadVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX);
+	gr6 = NVReadVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX);
+
+	NVWritePRMVIO(pNv, 0, NV_PRMVIO_MISC__WRITE, 0x67);
+	NVWriteVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX, 0x0);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX, 0x5);
 
 	/* store font in plane 0 */
-	NVWriteVgaSeq(pNv, 0, VGA_SEQ_PLANE_WRITE, 0x1);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_PLANE_READ, 0x0);
+	NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x1);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x0);
 	for (i = 0; i < 16384; i++)
 		if (save)
 			pNv->saved_vga_font[0][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
@@ -1179,8 +1161,8 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
 			MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[0][i]);
 
 	/* store font in plane 1 */
-	NVWriteVgaSeq(pNv, 0, VGA_SEQ_PLANE_WRITE, 0x2);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_PLANE_READ, 0x1);
+	NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x2);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x1);
 	for (i = 0; i < 16384; i++)
 		if (save)
 			pNv->saved_vga_font[1][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
@@ -1188,8 +1170,8 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
 			MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[1][i]);
 
 	/* store font in plane 2 */
-	NVWriteVgaSeq(pNv, 0, VGA_SEQ_PLANE_WRITE, 0x4);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_PLANE_READ, 0x2);
+	NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x4);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x2);
 	for (i = 0; i < 16384; i++)
 		if (save)
 			pNv->saved_vga_font[2][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
@@ -1197,8 +1179,8 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
 			MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[2][i]);
 
 	/* store font in plane 3 */
-	NVWriteVgaSeq(pNv, 0, VGA_SEQ_PLANE_WRITE, 0x8);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_PLANE_READ, 0x3);
+	NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x8);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x3);
 	for (i = 0; i < 16384; i++)
 		if (save)
 			pNv->saved_vga_font[3][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
@@ -1206,12 +1188,12 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
 			MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[3][i]);
 
 	/* restore control regs */
-	NVWritePRMVIO(pNv, 0, VGA_MISC_OUT_W, misc);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_PLANE_READ, gr4);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_MODE, gr5);
-	NVWriteVgaGr(pNv, 0, VGA_GFX_MISC, gr6);
-	NVWriteVgaSeq(pNv, 0, VGA_SEQ_PLANE_WRITE, seq2);
-	NVWriteVgaSeq(pNv, 0, VGA_SEQ_MEMORY_MODE, seq4);
+	NVWritePRMVIO(pNv, 0, NV_PRMVIO_MISC__WRITE, misc);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX, gr5);
+	NVWriteVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX, gr6);
+	NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
+	NVWriteVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
 
 	if (pNv->twoHeads)
 		NVBlankScreen(pNv, 1, false);
diff --git a/src/nv_proto.h b/src/nv_proto.h
index 0085f51..34adb17 100644
--- a/src/nv_proto.h
+++ b/src/nv_proto.h
@@ -99,8 +99,8 @@ void NVWriteVgaCrtc(NVPtr pNv, int head, uint8_t index, uint8_t value);
 uint8_t NVReadVgaCrtc(NVPtr pNv, int head, uint8_t index);
 void NVWriteVgaCrtc5758(NVPtr pNv, int head, uint8_t index, uint8_t value);
 uint8_t NVReadVgaCrtc5758(NVPtr pNv, int head, uint8_t index);
-uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint16_t port);
-void NVWritePRMVIO(NVPtr pNv, int head, uint16_t port, uint8_t value);
+uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint32_t reg);
+void NVWritePRMVIO(NVPtr pNv, int head, uint32_t reg, uint8_t value);
 void NVWriteVgaSeq(NVPtr pNv, int head, uint8_t index, uint8_t value);
 uint8_t NVReadVgaSeq(NVPtr pNv, int head, uint8_t index);
 void NVWriteVgaGr(NVPtr pNv, int head, uint8_t index, uint8_t value);
diff --git a/src/nvreg.h b/src/nvreg.h
index 43c6a1e..98a44e9 100644
--- a/src/nvreg.h
+++ b/src/nvreg.h
@@ -95,12 +95,15 @@
 #define NV_FIFO_OFFSET              0x00800000
 #define NV_FIFO_SIZE                0x00800000
 
-#define CRTC_INDEX_COLOR		0x3d4
-#define CRTC_DATA_COLOR			0x3d5
-
 #define NV_PMC_BOOT_0			0x00000000
 #define NV_PMC_ENABLE			0x00000200
 
+#define NV_VIO_VSE2			0x000003c3
+#define NV_VIO_SRX			0x000003c4
+
+#define NV_CIO_CRX__COLOR		0x000003d4
+#define NV_CIO_CR__COLOR		0x000003d5
+
 #define NV_PBUS_DEBUG_1			0x00001084
 #define NV_PBUS_DEBUG_4			0x00001098
 #define NV_PBUS_DEBUG_DUALHEAD_CTL	0x000010f0
@@ -114,6 +117,18 @@
 
 #define NV_PFIFO_RAMHT			0x00002210
 
+#define NV_PRMVIO_MISC__WRITE		0x000c03c2
+#define NV_PRMVIO_SRX			0x000c03c4
+#define NV_PRMVIO_SR			0x000c03c5
+	#define NV_VIO_SR_PLANE_MASK_INDEX	0x02
+	#define NV_VIO_SR_MEM_MODE_INDEX	0x04
+#define NV_PRMVIO_MISC__READ		0x000c03cc
+#define NV_PRMVIO_GRX			0x000c03ce
+#define NV_PRMVIO_GX			0x000c03cf
+	#define NV_VIO_GX_READ_MAP_INDEX	0x04
+	#define NV_VIO_GX_MODE_INDEX		0x05
+	#define NV_VIO_GX_MISC_INDEX		0x06
+
 #define NV_PFB_BOOT_0			0x00100000
 #define NV_PFB_CFG0			0x00100200
 #define NV_PFB_CFG1			0x00100204
@@ -162,6 +177,9 @@
 #	define NV_CRTC_FSEL_TVOUT2			(2<<8)
 #	define NV_CRTC_FSEL_OVERLAY			(1<<12)
 
+#define NV_PRMCIO_ARX			0x006013c0
+#define NV_PRMCIO_AR__WRITE		0x006013c0
+#define NV_PRMCIO_AR__READ		0x006013c1
 #define NV_PRMCIO_CRX__COLOR		0x006013d4
 #define NV_PRMCIO_CR__COLOR		0x006013d5
 	/* Standard VGA CRTC registers */
@@ -222,6 +240,7 @@
 	#define NV_CIO_CRE_59			0x59
 	#define NV_CIO_CRE_85			0x85
 	#define NV_CIO_CRE_86			0x86
+#define NV_PRMCIO_INP0__COLOR		0x006013da
 
 #define NV_RAMDAC_CURSOR_POS		0x00680300
 #define NV_RAMDAC_CURSOR_CTRL		0x00680320
@@ -380,6 +399,13 @@
 #define NV_RAMDAC_A24			0x00680A24
 #define NV_RAMDAC_A34			0x00680A34
 
+/* names fabricated from NV_USER_DAC info */
+#define NV_PRMDIO_PIXEL_MASK		0x006813c6
+	#define NV_PRMDIO_PIXEL_MASK_MASK	0xff
+#define NV_PRMDIO_READ_MODE_ADDRESS	0x006813c7
+#define NV_PRMDIO_WRITE_MODE_ADDRESS	0x006813c8
+#define NV_PRMDIO_PALETTE_DATA		0x006813c9
+
 #define NV_PGRAPH_DEBUG_0		0x00400080
 #define NV_PGRAPH_DEBUG_1		0x00400084
 #define NV_PGRAPH_DEBUG_2_NV04		0x00400088