Use symbolic define values where known

6 files changed, 108 insertions, 62 deletions

diff --git a/src/nv_bios.c b/src/nv_bios.c
index acac708..76fd6d0 100644
--- a/src/nv_bios.c
+++ b/src/nv_bios.c
@@ -33,7 +33,7 @@
 #endif
 
 
-/* FIXME: put these somewhere */
+/* these defines are made up */
 #define NV_CIO_CRE_44_HEADA 0x0
 #define NV_CIO_CRE_44_HEADB 0x3
 #define FEATURE_MOBILE 0x10
@@ -1402,7 +1402,7 @@ static bool init_tmds(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, init_exe
 	if (!(reg = get_tmds_index_reg(pScrn, mlv)))
 		return false;
 
-	nv32_wr(pScrn, reg, tmdsaddr | 0x10000);
+	nv32_wr(pScrn, reg, tmdsaddr | NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
 	value = (nv32_rd(pScrn, reg + 4) & mask) | data;
 	nv32_wr(pScrn, reg + 4, value);
 	nv32_wr(pScrn, reg, tmdsaddr);
@@ -1893,7 +1893,8 @@ static bool init_configure_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset,
 	if (bios->major_version > 2)
 		return false;
 
-	nv_idx_port_wr(pScrn, NV_VIO_SRX, 0x01, nv_idx_port_rd(pScrn, NV_VIO_SRX, 0x01) | 0x20);
+	nv_idx_port_wr(pScrn, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX,
+		       nv_idx_port_rd(pScrn, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
 
 	if (bios->data[meminitoffs] & 1)
 		seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
@@ -3865,10 +3866,10 @@ static void parse_bmp_structure(ScrnInfoPtr pScrn, bios_t *bios, unsigned int of
 	uint16_t legacy_scripts_offset, legacy_i2c_offset;
 
 	/* load needed defaults in case we can't parse this info */
-	pNv->dcb_table.i2c_write[0] = 0x3f;
-	pNv->dcb_table.i2c_read[0] = 0x3e;
-	pNv->dcb_table.i2c_write[1] = 0x37;
-	pNv->dcb_table.i2c_read[1] = 0x36;
+	pNv->dcb_table.i2c_write[0] = NV_CIO_CRE_DDC_WR__INDEX;
+	pNv->dcb_table.i2c_read[0] = NV_CIO_CRE_DDC_STATUS__INDEX;
+	pNv->dcb_table.i2c_write[1] = NV_CIO_CRE_DDC0_WR__INDEX;
+	pNv->dcb_table.i2c_read[1] = NV_CIO_CRE_DDC0_STATUS__INDEX;
 	bios->digital_min_front_porch = 0x4b;
 	bios->fmaxvco = 256000;
 	bios->fminvco = 128000;
diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index 1a17985..c7010d8 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -187,10 +187,10 @@ static void nv_crtc_cursor_set(xf86CrtcPtr crtc)
 
 	CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = cursor_start >> 17;
 	if (pNv->Architecture != NV_ARCH_04)
-		CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= 0x80;
+		CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] |= NV_CIO_CRE_HCUR_ASI;
 	CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = (cursor_start >> 11) << 2;
 	if (crtc->mode.Flags & V_DBLSCAN)
-		CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= 2;
+		CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= NV_CIO_CRE_HCUR_ADDR1_CUR_DBL;
 	CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = cursor_start >> 24;
 
 	NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_HCUR_ADDR0_INDEX, CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX]);
@@ -351,8 +351,8 @@ nv_crtc_dpms(xf86CrtcPtr crtc, int mode)
 
 	NVVgaSeqReset(pNv, nv_crtc->head, true);
 	/* Each head has it's own sequencer, so we can turn it off when we want */
-	seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, 0x01) & ~0x20);
-	NVWriteVgaSeq(pNv, nv_crtc->head, 0x1, seq1);
+	seq1 |= (NVReadVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
+	NVWriteVgaSeq(pNv, nv_crtc->head, NV_VIO_SR_CLOCK_INDEX, seq1);
 	crtc17 |= (NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX) & ~0x80);
 	usleep(10000);
 	NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_MODE_INDEX, crtc17);
@@ -463,15 +463,15 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus
 	/*
 	* Time Sequencer
 	*/
-	regp->Sequencer[0] = 0x00;
+	regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
 	/* 0x20 disables the sequencer */
 	if (mode->Flags & V_CLKDIV2)
-		regp->Sequencer[1] = 0x29;
+		regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
 	else
-		regp->Sequencer[1] = 0x21;
-	regp->Sequencer[2] = 0x0F;
-	regp->Sequencer[3] = 0x00;                     /* Font select */
-	regp->Sequencer[4] = 0x0E;                             /* Misc */
+		regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
+	regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
+	regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
+	regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
 
 	/*
 	* CRTC Controller
@@ -496,13 +496,13 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus
 	regp->CRTC[NV_CIO_CR_RSAL_INDEX]  = 0x00;
 	regp->CRTC[NV_CIO_CR_CELL_HT_INDEX]  = SetBitField(vertBlankStart,9:9,5:5)
 				| SetBit(6)
-				| ((mode->Flags & V_DBLSCAN) ? 0x80 : 0x00);
+				| (mode->Flags & V_DBLSCAN) * NV_CIO_CR_CELL_HT_SCANDBL;
 	regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
 	regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
 	regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
 	regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
-	regp->CRTC[0xe] = 0x00;
-	regp->CRTC[0xf] = 0x00;
+	regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
+	regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
 	regp->CRTC[NV_CIO_CR_VRS_INDEX] = Set8Bits(vertStart);
 	/* What is the meaning of bit5, it is empty in the vga spec. */
 	regp->CRTC[NV_CIO_CR_VRE_INDEX] = SetBitField(vertEnd,3:0,3:0) | SetBit(5);
@@ -548,15 +548,15 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus
 	/*
 	* Graphics Display Controller
 	*/
-	regp->Graphics[0] = 0x00;
-	regp->Graphics[1] = 0x00;
-	regp->Graphics[2] = 0x00;
-	regp->Graphics[3] = 0x00;
-	regp->Graphics[4] = 0x00;
-	regp->Graphics[5] = 0x40; /* 256 color mode */
-	regp->Graphics[6] = 0x05; /* map 64k mem + graphic mode */
-	regp->Graphics[7] = 0x0F;
-	regp->Graphics[8] = 0xFF;
+	regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
+	regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
+	regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
+	regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
+	regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
+	regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
+	regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
+	regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
+	regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
 
 	regp->Attribute[0]  = 0x00; /* standard colormap translation */
 	regp->Attribute[1]  = 0x01;
@@ -574,12 +574,12 @@ nv_crtc_mode_set_vga(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjus
 	regp->Attribute[13] = 0x0D;
 	regp->Attribute[14] = 0x0E;
 	regp->Attribute[15] = 0x0F;
-	regp->Attribute[16] = 0x01; /* Enable graphic mode */
+	regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
 	/* Non-vga */
-	regp->Attribute[17] = 0x00;
-	regp->Attribute[18] = 0x0F; /* enable all color planes */
-	regp->Attribute[19] = 0x00;
-	regp->Attribute[20] = 0x00;
+	regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
+	regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
+	regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
+	regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
 }
 
 /**
@@ -706,7 +706,7 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 	if (pNv->twoHeads)
 		regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
 
-	regp->config = 0x2; /* HSYNC mode */
+	regp->config = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
 
 	/* Some misc regs */
 	if (pNv->Architecture == NV_ARCH_40) {
@@ -957,10 +957,8 @@ nv_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 #if X_BYTE_ORDER == X_BIG_ENDIAN
 	/* turn on LFB swapping */
 	{
-		unsigned char tmp;
-
-		tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR);
-		tmp |= (1 << 7);
+		uint8_t tmp = NVReadVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR);
+		tmp |= NV_CIO_CRE_RCR_ENDIAN_BIG;
 		NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CRE_RCR, tmp);
 	}
 #endif
@@ -1032,7 +1030,7 @@ static void nv_crtc_prepare(xf86CrtcPtr crtc)
 	NVBlankScreen(pNv, nv_crtc->head, true);
 
 	/* Some more preperation. */
-	NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, 0x1); /* Go to non-vga mode/out of enhanced mode */
+	NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
 	if (pNv->Architecture == NV_ARCH_40) {
 		uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
 		NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
@@ -1346,7 +1344,7 @@ static void nv_crtc_load_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 		NVWriteVgaSeq(pNv, nv_crtc->head, i, regp->Sequencer[i]);
 
 	/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
-	NVWriteVgaCrtc(pNv, nv_crtc->head, 17, regp->CRTC[17] & ~0x80);
+	NVWriteVgaCrtc(pNv, nv_crtc->head, NV_CIO_CR_VRE_INDEX, regp->CRTC[NV_CIO_CR_VRE_INDEX] & ~0x80);
 
 	for (i = 0; i < 25; i++)
 		NVWriteVgaCrtc(pNv, nv_crtc->head, i, regp->CRTC[i]);
@@ -1398,7 +1396,7 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 
 		if (pNv->Architecture == NV_ARCH_40) {
 			uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
-			if (regp->config == 0x2) /* enhanced "horizontal only" non-vga mode */
+			if (regp->config == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
 				NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 | 0x10000);
 			else
 				NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
diff --git a/src/nv_hw.c b/src/nv_hw.c
index 4681f93..50bd481 100644
--- a/src/nv_hw.c
+++ b/src/nv_hw.c
@@ -220,19 +220,19 @@ uint8_t NVReadVgaAttr(NVPtr pNv, int head, uint8_t index)
 
 void NVVgaSeqReset(NVPtr pNv, int head, bool start)
 {
-	NVWriteVgaSeq(pNv, head, 0x0, start ? 0x1 : 0x3);
+	NVWriteVgaSeq(pNv, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
 }
 
 void NVVgaProtect(NVPtr pNv, int head, bool protect)
 {
-	uint8_t seq1 = NVReadVgaSeq(pNv, head, 0x1);
+	uint8_t seq1 = NVReadVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX);
 
 	if (protect) {
 		NVVgaSeqReset(pNv, head, true);
-		NVWriteVgaSeq(pNv, head, 0x01, seq1 | 0x20);
+		NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
 	} else {
 		/* Reenable sequencer, then turn on screen */
-		NVWriteVgaSeq(pNv, head, 0x01, seq1 & ~0x20);   /* reenable display */
+		NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);   /* reenable display */
 		NVVgaSeqReset(pNv, head, false);
 	}
 	NVSetEnablePalette(pNv, head, protect);
@@ -248,7 +248,8 @@ void NVLockVgaCrtc(NVPtr pNv, int head, bool lock)
 {
 	uint8_t cr11;
 
-	NVWriteVgaCrtc(pNv, head, NV_CIO_SR_LOCK_INDEX, lock ? 0x99 : 0x57);
+	NVWriteVgaCrtc(pNv, head, NV_CIO_SR_LOCK_INDEX,
+		       lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
 
 	cr11 = NVReadVgaCrtc(pNv, head, NV_CIO_CR_VRE_INDEX);
 	if (lock)
@@ -265,13 +266,13 @@ void NVBlankScreen(NVPtr pNv, int head, bool blank)
 	if (pNv->twoHeads)
 		NVSetOwner(pNv, head);
 
-	seq1 = NVReadVgaSeq(pNv, head, 0x1);
+	seq1 = NVReadVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX);
 
 	NVVgaSeqReset(pNv, head, true);
 	if (blank)
-		NVWriteVgaSeq(pNv, head, 0x1, seq1 | 0x20);
+		NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
 	else
-		NVWriteVgaSeq(pNv, head, 0x1, seq1 & ~0x20);
+		NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
 	NVVgaSeqReset(pNv, head, false);
 }
 
@@ -291,9 +292,11 @@ void nv_show_cursor(NVPtr pNv, int head, bool show)
 	int curctl1 = NVReadVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX);
 
 	if (show)
-		NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, curctl1 | 1);
+		NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX,
+			       curctl1 | NV_CIO_CRE_HCUR_ADDR1_ENABLE);
 	else
-		NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, curctl1 & ~1);
+		NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX,
+			       curctl1 & ~NV_CIO_CRE_HCUR_ADDR1_ENABLE);
 
 	if (pNv->Architecture == NV_ARCH_40)
 		nv_fix_nv40_hw_cursor(pNv, head);
@@ -1127,7 +1130,7 @@ void nv_save_restore_vga_fonts(ScrnInfoPtr pScrn, bool save)
 	int i;
 
 	NVSetEnablePalette(pNv, 0, true);
-	graphicsmode = NVReadVgaAttr(pNv, 0, 0x10) & 1;
+	graphicsmode = NVReadVgaAttr(pNv, 0, NV_CIO_AR_MODE_INDEX) & 1;
 	NVSetEnablePalette(pNv, 0, false);
 
 	if (graphicsmode)	/* graphics mode => framebuffer => no need to save */
diff --git a/src/nv_output.c b/src/nv_output.c
index 0c98c03..a3c5c71 100644
--- a/src/nv_output.c
+++ b/src/nv_output.c
@@ -59,7 +59,8 @@ nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 		testval = pNv->VBIOS.dactestval;
 
 	saved_rtest_ctrl = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset);
-	NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl & ~0x00010000);
+	NVWriteRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset,
+		      saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
 
 	if (pNv->NVArch >= 0x17) {
 		saved_powerctrl_2 = nvReadMC(pNv, NV_PBUS_POWERCTRL_2);
@@ -87,15 +88,19 @@ nv_load_detect(ScrnInfoPtr pScrn, struct nouveau_encoder *nv_encoder)
 	temp = NVReadRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset);
 	NVWriteRAMDAC(pNv, 0, NV_RAMDAC_OUTPUT + regoffset, temp | 1);
 
-	NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA, 1 << 31 | testval);
+	NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA,
+		      NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK | testval);
 	temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
-	NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL, temp | 0x1000);
+	NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL,
+		      temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
 	usleep(1000);
 
-	present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) & (1 << 28);
+	present = NVReadRAMDAC(pNv, 0, NV_RAMDAC_TEST_CONTROL + regoffset) &
+			NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI;
 
 	temp = NVReadRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL);
-	NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL, temp & 0xffffefff);
+	NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_CONTROL,
+		      temp & ~NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
 	NVWriteRAMDAC(pNv, head, NV_RAMDAC_TEST_DATA, 0);
 
 	/* bios does something more complex for restoring, but I think this is good enough */
@@ -654,7 +659,8 @@ static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv
 		regp = &pNv->ModeReg.crtc_reg[nv_crtc->head];
 
 		nv_crtc->fp_users |= 1 << nv_encoder->dcb->index;
-		NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control & ~0x20000022);
+		NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL,
+			      regp->fp_control & ~NV_PRAMDAC_FP_TG_CONTROL_OFF);
 	} else
 		for (i = 0; i < xf86_config->num_crtc; i++) {
 			nv_crtc = to_nouveau_crtc(xf86_config->crtc[i]);
@@ -663,7 +669,7 @@ static void dpms_update_fp_control(ScrnInfoPtr pScrn, struct nouveau_encoder *nv
 			nv_crtc->fp_users &= ~(1 << nv_encoder->dcb->index);
 			if (!nv_crtc->fp_users) {
 				/* cut the FP output */
-				regp->fp_control |= 0x20000022;
+				regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_OFF;
 				NVWriteRAMDAC(pNv, nv_crtc->head, NV_RAMDAC_FP_CONTROL, regp->fp_control);
 			}
 		}
diff --git a/src/nv_setup.c b/src/nv_setup.c
index 70930bf..5d73afc 100644
--- a/src/nv_setup.c
+++ b/src/nv_setup.c
@@ -484,14 +484,14 @@ NVCommonSetup(ScrnInfoPtr pScrn)
 
 				slaved_on_B = NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
 				if (slaved_on_B)
-					tvB = !(NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_LCD__INDEX) & 0x01);
+					tvB = !(NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_LCD__INDEX) & NV_CIO_CRE_LCD_LCD_SELECT);
 
 				NVSetOwner(pNv, 0);
 				NVLockVgaCrtc(pNv, 0, false);
 
 				slaved_on_A = NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
 				if (slaved_on_A)
-					tvA = !(NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_LCD__INDEX) & 0x01);
+					tvA = !(NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_LCD__INDEX) & NV_CIO_CRE_LCD_LCD_SELECT);
 
 				if (slaved_on_A && !tvA)
 					pNv->vtOWNER = 0x0;
diff --git a/src/nvreg.h b/src/nvreg.h
index 98a44e9..bbc0cc2 100644
--- a/src/nvreg.h
+++ b/src/nvreg.h
@@ -120,14 +120,23 @@
 #define NV_PRMVIO_MISC__WRITE		0x000c03c2
 #define NV_PRMVIO_SRX			0x000c03c4
 #define NV_PRMVIO_SR			0x000c03c5
+	#define NV_VIO_SR_RESET_INDEX		0x00
+	#define NV_VIO_SR_CLOCK_INDEX		0x01
 	#define NV_VIO_SR_PLANE_MASK_INDEX	0x02
+	#define NV_VIO_SR_CHAR_MAP_INDEX	0x03
 	#define NV_VIO_SR_MEM_MODE_INDEX	0x04
 #define NV_PRMVIO_MISC__READ		0x000c03cc
 #define NV_PRMVIO_GRX			0x000c03ce
 #define NV_PRMVIO_GX			0x000c03cf
+	#define NV_VIO_GX_SR_INDEX		0x00
+	#define NV_VIO_GX_SREN_INDEX		0x01
+	#define NV_VIO_GX_CCOMP_INDEX		0x02
+	#define NV_VIO_GX_ROP_INDEX		0x03
 	#define NV_VIO_GX_READ_MAP_INDEX	0x04
 	#define NV_VIO_GX_MODE_INDEX		0x05
 	#define NV_VIO_GX_MISC_INDEX		0x06
+	#define NV_VIO_GX_DONT_CARE_INDEX	0x07
+	#define NV_VIO_GX_BIT_MASK_INDEX	0x08
 
 #define NV_PFB_BOOT_0			0x00100000
 #define NV_PFB_CFG0			0x00100200
@@ -156,6 +165,8 @@
 #define NV_CRTC_INTR_EN_0		0x00600140
 #define NV_CRTC_START			0x00600800
 #define NV_CRTC_CONFIG			0x00600804
+	#define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA	1
+	#define NV_PCRTC_CONFIG_START_ADDRESS_HSYNC	2
 #define NV_CRTC_CURSOR_ADDRESS		0x0060080C
 #define NV_CRTC_CURSOR_CONFIG		0x00600810
 #	define NV_CRTC_CURSOR_CONFIG_ENABLE		(1 << 0)
@@ -180,6 +191,11 @@
 #define NV_PRMCIO_ARX			0x006013c0
 #define NV_PRMCIO_AR__WRITE		0x006013c0
 #define NV_PRMCIO_AR__READ		0x006013c1
+	#define	NV_CIO_AR_MODE_INDEX		0x10
+	#define NV_CIO_AR_OSCAN_INDEX		0x11
+	#define NV_CIO_AR_PLANE_INDEX		0x12
+	#define NV_CIO_AR_HPP_INDEX		0x13
+	#define NV_CIO_AR_CSEL_INDEX		0x14
 #define NV_PRMCIO_CRX__COLOR		0x006013d4
 #define NV_PRMCIO_CR__COLOR		0x006013d5
 	/* Standard VGA CRTC registers */
@@ -193,10 +209,13 @@
 	#define NV_CIO_CR_OVL_INDEX		0x07	/* overflow bits */
 	#define NV_CIO_CR_RSAL_INDEX		0x08	/* normally "preset row scan" */
 	#define NV_CIO_CR_CELL_HT_INDEX		0x09	/* cell height?! normally "max scan line" */
+		#define NV_CIO_CR_CELL_HT_SCANDBL	0x80
 	#define NV_CIO_CR_CURS_ST_INDEX		0x0a	/* cursor start */
 	#define NV_CIO_CR_CURS_END_INDEX	0x0b	/* cursor end */
 	#define NV_CIO_CR_SA_HI_INDEX		0x0c	/* screen start address high */
 	#define NV_CIO_CR_SA_LO_INDEX		0x0d	/* screen start address low */
+	#define NV_CIO_CR_TCOFF_HI_INDEX	0x0e	/* cursor offset high */
+	#define NV_CIO_CR_TCOFF_LO_INDEX	0x0f	/* cursor offset low */
 	#define NV_CIO_CR_VRS_INDEX		0x10	/* vertical retrace start */
 	#define NV_CIO_CR_VRE_INDEX		0x11	/* vertical retrace end */
 	#define NV_CIO_CR_VDE_INDEX		0x12	/* vertical display end */
@@ -212,6 +231,8 @@
 	#define NV_CIO_CRE_FF_INDEX		0x1b	/* fifo control */
 	#define NV_CIO_CRE_ENH_INDEX		0x1c	/* enhanced? */
 	#define NV_CIO_SR_LOCK_INDEX		0x1f	/* crtc lock */
+		#define	NV_CIO_SR_UNLOCK_RW_VALUE	0x57
+		#define	NV_CIO_SR_LOCK_VALUE		0x99
 	#define NV_CIO_CRE_FFLWM__INDEX		0x20	/* fifo low water mark */
 	#define NV_CIO_CRE_21			0x21	/* referred to by some .scp as `shadow lock' */
 	#define NV_CIO_CRE_LSR_INDEX		0x25	/* ? */
@@ -221,15 +242,24 @@
 	#define NV_CIO_CRE_HEB__INDEX		0x2d	/* horizontal extra bits? */
 	#define NV_CIO_CRE_HCUR_ADDR2_INDEX	0x2f	/* cursor */
 	#define NV_CIO_CRE_HCUR_ADDR0_INDEX	0x30		/* pixmap */
+		#define NV_CIO_CRE_HCUR_ASI		0x80
 	#define NV_CIO_CRE_HCUR_ADDR1_INDEX	0x31			/* address */
+		#define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL	0x02
+		#define NV_CIO_CRE_HCUR_ADDR1_ENABLE	0x01
 	#define NV_CIO_CRE_LCD__INDEX		0x33
+		#define NV_CIO_CRE_LCD_LCD_SELECT	0x01
+	#define NV_CIO_CRE_DDC0_STATUS__INDEX	0x36
+	#define NV_CIO_CRE_DDC0_WR__INDEX	0x37
 	#define NV_CIO_CRE_ILACE__INDEX		0x39	/* interlace */
 	#define NV_CIO_CRE_SCRATCH3__INDEX	0x3b
 	#define NV_CIO_CRE_SCRATCH4__INDEX	0x3c
+	#define NV_CIO_CRE_DDC_STATUS__INDEX	0x3e
+	#define NV_CIO_CRE_DDC_WR__INDEX	0x3f
 	#define NV_CIO_CRE_EBR_INDEX		0x41	/* extra bits ? (vertical) */
 	#define NV_CIO_CRE_44			0x44	/* head control */
 	#define NV_CIO_CRE_CSB			0x45
 	#define NV_CIO_CRE_RCR			0x46
+		#define NV_CIO_CRE_RCR_ENDIAN_BIG	0x80;
 	#define NV_CIO_CRE_47			0x47	/* extended fifo lwm, used on nv30+ */
 	#define NV_CIO_CRE_4B			0x4b	/* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */
 	#define NV_CIO_CRE_52			0x52
@@ -308,7 +338,11 @@
 #define NV_RAMDAC_594			0x00680594
 #define NV_RAMDAC_GENERAL_CONTROL	0x00680600
 #define NV_RAMDAC_TEST_CONTROL		0x00680608
+	#define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED	(1 << 12)
+	#define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF	(1 << 16)
+	#define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI	(1 << 28)
 #define NV_RAMDAC_TEST_DATA		0x00680610
+	#define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK	(1 << 31)
 #define NV_RAMDAC_630			0x00680630
 /* This register is similar to TEST_CONTROL in the style of values */
 #define NV_RAMDAC_670			0x00680670
@@ -366,6 +400,9 @@
 #	define NV_RAMDAC_FP_CONTROL_WIDTH_12			(1 << 24)
 #	define NV_RAMDAC_FP_CONTROL_DISPEN_POS			(1 << 28)
 #	define NV_RAMDAC_FP_CONTROL_DISPEN_DISABLE		(2 << 28)
+	#define NV_PRAMDAC_FP_TG_CONTROL_OFF		(NV_RAMDAC_FP_CONTROL_DISPEN_DISABLE |	\
+							 NV_RAMDAC_FP_CONTROL_HSYNC_DISABLE |	\
+							 NV_RAMDAC_FP_CONTROL_VSYNC_DISABLE)
 #define NV_RAMDAC_FP_850		0x00680850
 #define NV_RAMDAC_FP_85C		0x0068085c
 
@@ -386,6 +423,7 @@
 #define NV30_RAMDAC_894			0x00680894
 #define NV30_RAMDAC_89C			0x0068089C
 
+/* see NV_PRAMDAC_INDIR_TMDS in rules.xml */
 #define NV_RAMDAC_FP_TMDS_CONTROL	0x006808b0
 #	define NV_RAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE	(1<<16)
 #define NV_RAMDAC_FP_TMDS_DATA		0x006808b4