diff options
| author | Jammy Zhou <Jammy.Zhou@amd.com> | 2015-05-06 18:45:57 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2015-05-07 13:11:11 -0400 |
| commit | 3f2e298f21bd9a567e02e2b593cbe2c752768496 (patch) | |
| tree | 9f43229e43252f2067d9c86e958170c42b35acef | |
| parent | 68495c9bf9ff6554739fef053fc7828474212a1a (diff) | |
amdgpu: remove AMDGPU_GEM_CREATE_CPU_GTT_UC
Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | include/drm/amdgpu_drm.h | 7 | ||||
| -rw-r--r-- | tests/amdgpu/basic_tests.c | 19 |
2 files changed, 10 insertions, 16 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 566eb072..415a861e 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -73,15 +73,12 @@ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) /* Flag that CPU access will not work, this VRAM domain is invisible */ #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) -/* Flag that un-cached attributes should be used for GTT */ -#define AMDGPU_GEM_CREATE_CPU_GTT_UC (1 << 2) /* Flag that USWC attributes should be used for GTT */ -#define AMDGPU_GEM_CREATE_CPU_GTT_WC (1 << 3) +#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) /* Flag mask for GTT domain_flags */ #define AMDGPU_GEM_CREATE_CPU_GTT_MASK \ - (AMDGPU_GEM_CREATE_CPU_GTT_WC | \ - AMDGPU_GEM_CREATE_CPU_GTT_UC | \ + (AMDGPU_GEM_CREATE_CPU_GTT_USWC | \ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \ AMDGPU_GEM_CREATE_NO_CPU_ACCESS) diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index c8c759f4..6654e588 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -146,7 +146,7 @@ static void amdgpu_memory_alloc(void) bo = gpu_mem_alloc(device_handle, 4096, 4096, AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_CPU_GTT_WC, + AMDGPU_GEM_CREATE_CPU_GTT_USWC, &bo_mc); r = amdgpu_bo_free(bo); @@ -345,8 +345,7 @@ static void amdgpu_command_submission_sdma_write_linear(void) uint64_t bo_mc; volatile uint32_t *bo_cpu; int i, j, r, loop; - uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC, - AMDGPU_GEM_CREATE_CPU_GTT_WC}; + uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -365,7 +364,7 @@ static void amdgpu_command_submission_sdma_write_linear(void) CU_ASSERT_NOT_EQUAL(resources, NULL); loop = 0; - while(loop < 3) { + while(loop < 2) { /* allocate UC bo for sDMA use */ bo = gpu_mem_alloc(device_handle, sdma_write_length * sizeof(uint32_t), @@ -428,8 +427,7 @@ static void amdgpu_command_submission_sdma_const_fill(void) uint64_t bo_mc; volatile uint32_t *bo_cpu; int i, j, r, loop; - uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC, - AMDGPU_GEM_CREATE_CPU_GTT_WC}; + uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -448,7 +446,7 @@ static void amdgpu_command_submission_sdma_const_fill(void) CU_ASSERT_NOT_EQUAL(resources, NULL); loop = 0; - while(loop < 3) { + while(loop < 2) { /* allocate UC bo for sDMA use */ bo = gpu_mem_alloc(device_handle, sdma_write_length, 4096, @@ -509,8 +507,7 @@ static void amdgpu_command_submission_sdma_copy_linear(void) uint64_t bo1_mc, bo2_mc; volatile unsigned char *bo1_cpu, *bo2_cpu; int i, j, r, loop1, loop2; - uint64_t gtt_flags[3] = {0, AMDGPU_GEM_CREATE_CPU_GTT_UC, - AMDGPU_GEM_CREATE_CPU_GTT_WC}; + uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -530,8 +527,8 @@ static void amdgpu_command_submission_sdma_copy_linear(void) loop1 = loop2 = 0; /* run 9 circle to test all mapping combination */ - while(loop1 < 3) { - while(loop2 < 3) { + while(loop1 < 2) { + while(loop2 < 2) { /* allocate UC bo1for sDMA use */ bo1 = gpu_mem_alloc(device_handle, sdma_write_length, 4096, |