diff options
| author | Pan Xiuli <xiuli.pan@intel.com> | 2017-04-06 16:26:36 +0800 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2017-09-22 16:25:20 +0800 |
| commit | 307e30b4f3f5682f0d5770f59454a66860b70e3c (patch) | |
| tree | da1812d78a40668d860ea10b68634524605e03c2 | |
| parent | fa82b1d1161b3c96e45444af03d8b98a951875fc (diff) | |
Backend: Fix flag and subflag seting for src 3 instruction
Before gen8, src 3 instruction has different flag and subflag bits
V2: Fix the sub flag bit.
Signed-off-by: Pan Xiuli <xiuli.pan@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
| -rw-r--r-- | backend/src/backend/gen75_encoder.cpp | 10 | ||||
| -rw-r--r-- | backend/src/backend/gen7_encoder.cpp | 10 | ||||
| -rw-r--r-- | backend/src/backend/gen7_instruction.hpp | 5 |
3 files changed, 19 insertions, 6 deletions
diff --git a/backend/src/backend/gen75_encoder.cpp b/backend/src/backend/gen75_encoder.cpp index b82cc431..06cca3c9 100644 --- a/backend/src/backend/gen75_encoder.cpp +++ b/backend/src/backend/gen75_encoder.cpp @@ -53,8 +53,14 @@ namespace gbe gen7_insn->header.quarter_control = this->curr.quarterControl; gen7_insn->bits1.ia1.nib_ctrl = this->curr.nibControl; gen7_insn->header.mask_control = this->curr.noMask; - gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag; - gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag; + if (insn->header.opcode == GEN_OPCODE_MAD || insn->header.opcode == GEN_OPCODE_LRP) + { + gen7_insn->bits1.da3src.flag_reg_nr = this->curr.flag; + gen7_insn->bits1.da3src.flag_sub_reg_nr = this->curr.subFlag; + } else { + gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag; + gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag; + } if (this->curr.predicate != GEN_PREDICATE_NONE) { gen7_insn->header.predicate_control = this->curr.predicate; gen7_insn->header.predicate_inverse = this->curr.inversePredicate; diff --git a/backend/src/backend/gen7_encoder.cpp b/backend/src/backend/gen7_encoder.cpp index 4b2cd9ab..d526f5dd 100644 --- a/backend/src/backend/gen7_encoder.cpp +++ b/backend/src/backend/gen7_encoder.cpp @@ -46,8 +46,14 @@ namespace gbe gen7_insn->header.quarter_control = this->curr.quarterControl; gen7_insn->bits1.ia1.nib_ctrl = this->curr.nibControl; gen7_insn->header.mask_control = this->curr.noMask; - gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag; - gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag; + if (insn->header.opcode == GEN_OPCODE_MAD || insn->header.opcode == GEN_OPCODE_LRP) + { + gen7_insn->bits1.da3src.flag_reg_nr = this->curr.flag; + gen7_insn->bits1.da3src.flag_sub_reg_nr = this->curr.subFlag; + } else { + gen7_insn->bits2.ia1.flag_reg_nr = this->curr.flag; + gen7_insn->bits2.ia1.flag_sub_reg_nr = this->curr.subFlag; + } if (this->curr.predicate != GEN_PREDICATE_NONE) { gen7_insn->header.predicate_control = this->curr.predicate; gen7_insn->header.predicate_inverse = this->curr.inversePredicate; diff --git a/backend/src/backend/gen7_instruction.hpp b/backend/src/backend/gen7_instruction.hpp index 7d7eadaa..c985fb81 100644 --- a/backend/src/backend/gen7_instruction.hpp +++ b/backend/src/backend/gen7_instruction.hpp @@ -142,8 +142,9 @@ union Gen7NativeInstruction struct { uint32_t dest_reg_file:1; - uint32_t flag_subreg_num:1; - uint32_t pad0:2; + uint32_t flag_sub_reg_nr:1; + uint32_t flag_reg_nr:1; + uint32_t pad0:1; uint32_t src0_abs:1; uint32_t src0_negate:1; uint32_t src1_abs:1; |