diff options
| author | Pan Xiuli <xiuli.pan@intel.com> | 2016-09-02 16:50:49 +0800 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2016-10-21 12:34:34 +0800 |
| commit | fb8dd160cb5db7d82f25514071466e90224e1e35 (patch) | |
| tree | 10e6ea7415a948c12cd17c8f9384959c39ed81d1 | |
| parent | 5d1e665d9de72b45063a9c6aa49a14140e79c532 (diff) | |
Backend: Fix simd shuffle base address
In genregister subnr is in byte, this will not infulence register that
is 32 align which subnr is 0, but will get wrong base address for simd8
HF or W type register if they have nozero subnr.
Signed-off-by: Pan Xiuli <xiuli.pan@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
| -rw-r--r-- | backend/src/backend/gen8_context.cpp | 2 | ||||
| -rw-r--r-- | backend/src/backend/gen_context.cpp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/backend/src/backend/gen8_context.cpp b/backend/src/backend/gen8_context.cpp index 58098354..a520e618 100644 --- a/backend/src/backend/gen8_context.cpp +++ b/backend/src/backend/gen8_context.cpp @@ -328,7 +328,7 @@ namespace gbe assert(insn.opcode == SEL_OP_SIMD_SHUFFLE); assert (src1.file != GEN_IMMEDIATE_VALUE); - uint32_t base = src0.nr * 32 + src0.subnr * 4; + uint32_t base = src0.nr * 32 + src0.subnr; GenRegister baseReg = GenRegister::immuw(base); const GenRegister a0 = GenRegister::addr8(0); p->ADD(a0, GenRegister::unpacked_uw(src1.nr, src1.subnr / typeSize(GEN_TYPE_UW)), baseReg); diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp index 33f10267..6afa4709 100644 --- a/backend/src/backend/gen_context.cpp +++ b/backend/src/backend/gen_context.cpp @@ -702,7 +702,7 @@ namespace gbe assert(insn.opcode == SEL_OP_SIMD_SHUFFLE); assert (src1.file != GEN_IMMEDIATE_VALUE); - uint32_t base = src0.nr * 32 + src0.subnr * 4; + uint32_t base = src0.nr * 32 + src0.subnr; GenRegister baseReg = GenRegister::immuw(base); const GenRegister a0 = GenRegister::addr8(0); uint32_t simd = p->curr.execWidth; |