diff options
author | Guo Yejun <yejun.guo@intel.com> | 2016-09-30 10:38:31 +0800 |
---|---|---|
committer | Yang Rong <rong.r.yang@intel.com> | 2016-10-21 12:42:31 +0800 |
commit | a8d6d737b6200e1746a14e76a09dc2a7dfdd6634 (patch) | |
tree | c636e232d677aedf63de689dc5b7ba751539218e | |
parent | 9115e8508490c5b99176dc0217c124d490c9a547 (diff) |
change PCI_CHIP_BROXTON_P to PCI_CHIP_BROXTON_0 to unify the naming
Signed-off-by: Guo Yejun <yejun.guo@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
-rw-r--r-- | src/cl_device_data.h | 4 | ||||
-rw-r--r-- | src/cl_device_id.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/cl_device_data.h b/src/cl_device_data.h index 3e6ac91d..4ee4ca37 100644 --- a/src/cl_device_data.h +++ b/src/cl_device_data.h @@ -297,13 +297,13 @@ #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || IS_SKL_GT2(devid) || IS_SKL_GT3(devid) || IS_SKL_GT4(devid)) /* BXT */ -#define PCI_CHIP_BROXTON_P 0x5A84 /* Intel(R) BXT-P for mobile desktop */ +#define PCI_CHIP_BROXTON_0 0x5A84 #define PCI_CHIP_BROXTON_1 0x5A85 #define PCI_CHIP_BROXTON_2 0x1A84 #define PCI_CHIP_BROXTON_3 0x1A85 #define IS_BROXTON(devid) \ - (devid == PCI_CHIP_BROXTON_P || \ + (devid == PCI_CHIP_BROXTON_0 || \ devid == PCI_CHIP_BROXTON_1 || \ devid == PCI_CHIP_BROXTON_2 || \ devid == PCI_CHIP_BROXTON_3) diff --git a/src/cl_device_id.c b/src/cl_device_id.c index 957b9531..d856cfeb 100644 --- a/src/cl_device_id.c +++ b/src/cl_device_id.c @@ -635,8 +635,8 @@ skl_gt4_break: cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id); break; - case PCI_CHIP_BROXTON_P: - DECL_INFO_STRING(bxt18eu_break, intel_bxt18eu_device, name, "Intel(R) HD Graphics Broxton-P"); + case PCI_CHIP_BROXTON_0: + DECL_INFO_STRING(bxt18eu_break, intel_bxt18eu_device, name, "Intel(R) HD Graphics Broxton 0"); case PCI_CHIP_BROXTON_2: DECL_INFO_STRING(bxt18eu_break, intel_bxt18eu_device, name, "Intel(R) HD Graphics Broxton 2"); bxt18eu_break: |