diff options
| author | Francisco Jerez <currojerez@riseup.net> | 2015-12-04 15:34:14 +0200 |
|---|---|---|
| committer | Yang Rong <rong.r.yang@intel.com> | 2016-01-05 15:20:49 +0800 |
| commit | aecf78ef4cfc649e5faf9ef613567a5d98ff480e (patch) | |
| tree | 673eb5b628f8a14087feef98482e6945c5107d7c | |
| parent | 4f0721d1c146b65f940bc8a539007daeec431024 (diff) | |
SKL: Use kernel-defined MOCS values instead of assuming hardware defaults.
Reported to fix fix a ~50% performance regression (in OpenCV 3.0 and
Luxmark 2.1 among others) with v4.3 kernels on Gen9 hardware.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92975
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
| -rw-r--r-- | src/intel/intel_gpgpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c index 04c67f80..dfe2af38 100644 --- a/src/intel/intel_gpgpu.c +++ b/src/intel/intel_gpgpu.c @@ -282,9 +282,9 @@ intel_gpgpu_get_cache_ctrl_gen8() static uint32_t intel_gpgpu_get_cache_ctrl_gen9() { - //Pre-defined cache control registers 9: + //Kernel-defined cache control registers 2: //L3CC: WB; LeCC: WB; TC: LLC/eLLC; - return (0x9 << 1); + return (0x2 << 1); } static void |