diff options
author | Ruiling Song <ruiling.song@intel.com> | 2015-10-22 16:28:27 +0800 |
---|---|---|
committer | Yang Rong <rong.r.yang@intel.com> | 2015-12-18 14:53:53 +0800 |
commit | a34d7a42d0317bc6a4d8c650265e14cb9c58f681 (patch) | |
tree | cbd6bf8c5e9b5b256d1c552a57c44a1e08979db8 | |
parent | 9822ca0bfe8b2a4ace2ae5defb53155b68769ab2 (diff) |
GBE: Fix unaligned load/store issues.
1. need support float.
2. get correct element type.
3. should use ir::TYPE_U8 for byte store.
Signed-off-by: Ruiling Song <ruiling.song@intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>
-rw-r--r-- | backend/src/llvm/llvm_gen_backend.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index 49054152..7c5b8a09 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -4334,7 +4334,6 @@ namespace gbe void GenWriter::emitUnalignedDQLoadStore(ir::Register ptr, Value *llvmValues, ir::AddressSpace addrSpace, ir::Register bti, bool isLoad, bool dwAligned, bool fixedBTI) { Type *llvmType = llvmValues->getType(); - const ir::Type type = getType(ctx, llvmType); unsigned byteSize = getTypeByteSize(unit, llvmType); Type *elemType = llvmType; @@ -4344,6 +4343,7 @@ namespace gbe elemType = vectorType->getElementType(); elemNum = vectorType->getNumElements(); } + const ir::Type type = getType(ctx, elemType); vector<ir::Register> tupleData; for (uint32_t elemID = 0; elemID < elemNum; ++elemID) { @@ -4386,7 +4386,7 @@ namespace gbe ctx.LOADI(ir::TYPE_S32, offset, immIndex); ctx.ADD(ir::TYPE_S32, addr, ptr, offset); } - ctx.STORE(type, addr, addrSpace, dwAligned, fixedBTI, bti, reg); + ctx.STORE(ir::TYPE_U8, addr, addrSpace, dwAligned, fixedBTI, bti, reg); } } } @@ -4440,9 +4440,10 @@ namespace gbe else ptr = pointer; + unsigned primitiveBits = scalarType->getPrimitiveSizeInBits(); if (!dwAligned - && (scalarType == IntegerType::get(I.getContext(), 64) - || scalarType == IntegerType::get(I.getContext(), 32)) + && (primitiveBits == 64 + || primitiveBits == 32) ) { emitUnalignedDQLoadStore(ptr, llvmValues, addrSpace, btiReg, isLoad, dwAligned, fixedBTI); return; |